MLA
Dr. Sarabjeet Kaur; Aditya Soraut; Amit Verma; Abhishek Kumar. (Volume. 3 Issue. 4, April - 2025) "Digital Sign Calculator Verification and Implementation of Verilog HDL via FPGA Simulation." International Journal of Modern Science and Research Technology (IJMSRT), www.ijmsrt.com. , PP :- 140-145.
APA
Dr. Sarabjeet Kaur; Aditya Soraut; Amit Verma; Abhishek Kumar. "Digital Sign Calculator Verification and Implementation of Verilog HDL via FPGA Simulation." Volume. 3 Issue. 4, April - 2025 International Journal of Modern Science and Research Technology (IJMSRT), www.ijmsrt.com. PP :- 140-145.