The importance of hardware accelerators for arithmetic operations has been highlighted by the growing need for high-performance and low-power digital systems. In embedded systems and digital signal processing (DSP), multipliers are essential parts. The design and FPGA implementation of a 4-bit signed multiplier with two's complement representation are presented in this paper. The architecture optimizes efficiency and resource utilization by combining partial product generation and adding approaches. Verilog HDL is used for implementation on a Xilinx FPGA, and the synthesis results are examined in terms of power, time, and area.